This design is targeted for xczu5ev board (part number: xczu5ev-sfvc784-1-e)

Zynq UltraScale+ Design Summary

Device	xczu5ev
SpeedGrade	-1
Part	xczu5ev-sfvc784-1-e
Description	Zynq UltraScale+ PS Configuration Report
Vendor	Xilinx

MIO Table View

MIO Pin	Peripheral	Signal	IO Type	Speed	Pullup	Direction	Drive Strength(mA)
MIO 0	Quad SPI Flash	sclk_out	cmos	slow	disable	out	12
MIO 1	Quad SPI Flash	miso_mo1	cmos	fast	pullup	inout	8
MIO 2	Quad SPI Flash	mo2	cmos	fast	pullup	inout	8
MIO 3	Quad SPI Flash	mo3	cmos	fast	pullup	inout	8
MIO 4	Quad SPI Flash	mosi_mi0	cmos	fast	pullup	inout	8
MIO 5	Quad SPI Flash	n_ss_out	cmos	slow	pullup	out	8
MIO 6	Feedback Clk	clk_for_lpbk	cmos	fast	pullup	out	12
MIO 7	PCIE	reset_n	cmos	slow	pullup	out	12
MIO 8	I2C 1	scl_out	cmos	slow	disable	inout	4
MIO 9	I2C 1	sda_out	cmos	slow	disable	inout	4
MIO 10	GPIO0 MIO	gpio0[10]	cmos	slow	disable	inout	12
MIO 11	GPIO0 MIO	gpio0[11]	cmos	slow	disable	inout	12
MIO 12	SPI 0	sclk_out	cmos	slow	pullup	inout	12
MIO 13	GPIO0 MIO	gpio0[13]	cmos	slow	disable	inout	12
MIO 14	SPI 0	n_ss_out[1]	cmos	slow	disable	out	4
MIO 15	SPI 0	n_ss_out[0]	cmos	slow	disable	inout	4
MIO 16	SPI 0	miso	cmos	slow	disable	inout	12
MIO 17	SPI 0	mosi	cmos	slow	disable	inout	12
MIO 18	UART 0	rxd	cmos	fast	disable	in	12
MIO 19	UART 0	txd	cmos	slow	pullup	out	12
MIO 20	GPIO0 MIO	gpio0[20]	cmos	slow	pullup	inout	12
MIO 21	GPIO0 MIO	gpio0[21]	cmos	slow	pulldown	inout	12
MIO 22	I2C 0	scl_out	cmos	slow	disable	inout	4
MIO 23	I2C 0	sda_out	cmos	slow	disable	inout	4
MIO 24	GPIO0 MIO	gpio0[24]	cmos	slow	disable	inout	12
MIO 25	GPIO0 MIO	gpio0[25]	cmos	slow	pullup	inout	12
MIO 26	Gem 0	rgmii_tx_clk	cmos	slow	disable	out	8
MIO 27	Gem 0	rgmii_txd[0]	cmos	slow	disable	out	8
MIO 28	Gem 0	rgmii_txd[1]	cmos	slow	disable	out	8
MIO 29	Gem 0	rgmii_txd[2]	cmos	slow	disable	out	8
MIO 30	Gem 0	rgmii_txd[3]	cmos	slow	disable	out	8
MIO 31	Gem 0	rgmii_tx_ctl	cmos	slow	disable	out	8
MIO 32	Gem 0	rgmii_rx_clk	cmos	fast	pulldown	in	12
MIO 33	Gem 0	rgmii_rxd[0]	cmos	fast	pulldown	in	12
MIO 34	Gem 0	rgmii_rxd[1]	cmos	fast	pulldown	in	12
MIO 35	Gem 0	rgmii_rxd[2]	cmos	fast	pulldown	in	12
MIO 36	Gem 0	rgmii_rxd[3]	cmos	fast	pulldown	in	12
MIO 37	Gem 0	rgmii_rx_ctl	cmos	fast	pulldown	in	12
MIO 38	GPIO1 MIO	gpio1[38]	cmos	slow	disable	inout	12
MIO 39	SD 1	sdio1_data_out[4]	cmos	slow	disable	inout	4
MIO 40	SD 1	sdio1_data_out[5]	cmos	fast	pullup	inout	12
MIO 41	SD 1	sdio1_data_out[6]	cmos	fast	pullup	inout	12
MIO 42	SD 1	sdio1_data_out[7]	cmos	fast	pullup	inout	12
MIO 43	SD 1	sdio1_bus_pow	cmos	slow	disable	out	4
MIO 44	GPIO1 MIO	gpio1[44]	cmos	slow	disable	inout	12
MIO 45	SD 1	sdio1_cd_n	cmos	fast	disable	in	12
MIO 46	SD 1	sdio1_data_out[0]	cmos	fast	pullup	inout	12
MIO 47	SD 1	sdio1_data_out[1]	cmos	fast	pullup	inout	12
MIO 48	SD 1	sdio1_data_out[2]	cmos	fast	pullup	inout	12
MIO 49	SD 1	sdio1_data_out[3]	cmos	fast	pullup	inout	12
MIO 50	SD 1	sdio1_cmd_out	cmos	fast	pullup	inout	12
MIO 51	SD 1	sdio1_clk_out	cmos	fast	pullup	out	12
MIO 52	USB 0	ulpi_clk_in	schmitt	fast	disable	in	12
MIO 53	USB 0	ulpi_dir	schmitt	fast	pulldown	in	12
MIO 54	USB 0	ulpi_tx_data[2]	schmitt	fast	disable	inout	12
MIO 55	USB 0	ulpi_nxt	schmitt	fast	pulldown	in	12
MIO 56	USB 0	ulpi_tx_data[0]	schmitt	fast	disable	inout	12
MIO 57	USB 0	ulpi_tx_data[1]	schmitt	fast	disable	inout	12
MIO 58	USB 0	ulpi_stp	cmos	fast	pullup	out	12
MIO 59	USB 0	ulpi_tx_data[3]	schmitt	fast	disable	inout	12
MIO 60	USB 0	ulpi_tx_data[4]	schmitt	fast	disable	inout	12
MIO 61	USB 0	ulpi_tx_data[5]	schmitt	fast	disable	inout	12
MIO 62	USB 0	ulpi_tx_data[6]	schmitt	fast	disable	inout	12
MIO 63	USB 0	ulpi_tx_data[7]	schmitt	fast	disable	inout	12
MIO 64	USB 1	ulpi_clk_in	schmitt	fast	disable	in	12
MIO 65	USB 1	ulpi_dir	schmitt	fast	pulldown	in	12
MIO 66	USB 1	ulpi_tx_data[2]	schmitt	fast	disable	inout	12
MIO 67	USB 1	ulpi_nxt	schmitt	fast	pulldown	in	12
MIO 68	USB 1	ulpi_tx_data[0]	schmitt	fast	disable	inout	12
MIO 69	USB 1	ulpi_tx_data[1]	schmitt	fast	disable	inout	12
MIO 70	USB 1	ulpi_stp	cmos	fast	pullup	out	12
MIO 71	USB 1	ulpi_tx_data[3]	schmitt	fast	disable	inout	12
MIO 72	USB 1	ulpi_tx_data[4]	schmitt	fast	disable	inout	12
MIO 73	USB 1	ulpi_tx_data[5]	schmitt	fast	disable	inout	12
MIO 74	USB 1	ulpi_tx_data[6]	schmitt	fast	disable	inout	12
MIO 75	USB 1	ulpi_tx_data[7]	schmitt	fast	disable	inout	12
MIO 76	MDIO 0	gem0_mdc	cmos	slow	pullup	out	4
MIO 77	MDIO 0	gem0_mdio_out	cmos	slow	disable	inout	4

PS Clocks information

PSS REF CLK : 30.000

Name	Source	Input Frequency (MHz)
APLL	PSS_REF_CLK	2400.000
DPLL	PSS_REF_CLK	2130.000
VPLL	PSS_REF_CLK	3000.000
RPLL	PSS_REF_CLK	1590.000
IOPLL	PSS_REF_CLK	3000.000

Peripheral	Requested Frequency (MHz)	Source	Actual Frequency (MHz)
GEM0 freq (MHz)	125	IOPLL	125.000000
USB0 freq (MHz)	250	IOPLL	250.000000
USB1 freq (MHz)	250	IOPLL	250.000000
QSPI freq (MHz)	250	IOPLL	250.000000
SDIO1 freq (MHz)	200	IOPLL	187.500000
UART0 freq (MHz)	100	IOPLL	100.000000
I2C0 freq (MHz)	100	IOPLL	100.000000
I2C1 freq (MHz)	100	IOPLL	100.000000
SPI0 freq (MHz)	200	RPLL	198.750000
CPU_R5 freq (MHz)	500	IOPLL	500.000000
IOU_SWITCH freq (MHz)	267	RPLL	265.000000
LPD_SWITCH freq (MHz)	500	IOPLL	500.000000
LPD_LSBUS freq (MHz)	100	IOPLL	100.000000
GEM_TSU freq (MHz)	250	IOPLL	250.000000
TIMESTAMP freq (MHz)	100	PSS_REF_CLK	30.000000
PSU__CRL_APB__USB3_REF_CTRL__freqmhz	20	IOPLL	20.000000
PCAP freq (MHz)	200	IOPLL	187.500000
DBG_LPD freq (MHz)	250	IOPLL	250.000000
ADMA freq (MHz)	500	IOPLL	500.000000
PL0 freq (MHz)	100	IOPLL	100.000000
AMS freq (MHz)	50	IOPLL	50.000000
ACPU freq (MHz)	1200	APLL	1200.000000
DBG FPD freq (MHz)	250	IOPLL	250.000000
DP VIDEO freq (MHz)	300	VPLL	300.000000
DP AUDIO freq (MHz)	25	RPLL	24.843750
DP STC freq (MHz)	27	RPLL	26.500000
PCIE freq (MHz)	250	IOPLL	250.000000
DDR_CTRL freq MHz)	533.000	DPLL	532.500000
GPU freq (MHz)	600	IOPLL	500.000000
GDMA freq (MHz)	600	APLL	600.000000
DPDMA freq (MHz)	600	APLL	600.000000
TOPSW_MAIN freq (MHz)	533.333	DPLL	532.500000
TOPSW_LSBUS freq (MHz)	100	IOPLL	100.000000
DBG TSTMP freq (MHz)	250	IOPLL	250.000000

DDR Memory information

Parameter name	Value	Description
ENABLE	1	Enable the PS DDR Controller
DDR Interface freq (MHz)	1066	--
MEMORY TYPE	DDR 4	Type of memory interface
DM DBI	UDIMM
BUS WIDTH	64 Bit	Data width of DDR interface, not including ECC data width
ECC	Disabled	Enables error correction code support
SPEED BIN	DDR4_2133P	Speed Bin
CL	15	Column Access Strobe (CAS) latency in memory clock cycles. It refers to the amount of time it takes for data to appear on the pins of the memory module
CWL	14	CAS write latency setting in memory clock cycles
DDR AL	0	Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
T RCD	15	tRCD. Row address to column address delay time. It is the time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
T RP	15	Precharge Time is the number of clock cycles needed to terminate access to an open row of memory and open access to the next row
T RC	47.06	Row cycle time (ns)
T RAS MIN	33	Minimum number of memory clock cycles required between an Active and Precharge command
T FAW	30.0	Determines the number of activates that can be performed within a certain window of time
DRAM WIDTH	8 Bits	Width of individual DRAM components
DEVICE CAPACITY	4096 MBits	Storage capacity of individual DRAM components
BG ADDR COUNT	2	Number of bank group address pins
RANK ADDR COUNT	0	Dual-rank or dual-DIMM configuration of DRAM. Addressed using two chip-select bits (CS_N)
BANK ADDR COUNT	2	Number of bank address pins
ROW ADDR COUNT	15	Number of row address pins
COL ADDR COUNT	10	Number of column address bits
C_DDR_RAM_HIGHADDR	0xFFFFFFFF	--

GT lanes information

Protocol	GT lane#	Ref Clk Sel	Ref freq (MHz)
PCIe	GT Lane0	Ref Clk0	100
USB0	GT Lane1	Ref Clk0	100
DP	GT Lane2	Ref Clk2	108