--- include/dt-bindings/gpio/gpio.h	1970-01-01 02:00:00.000000000 +0200
+++ include/dt-bindings/gpio/gpio.h	2021-11-09 17:10:27.966356000 +0200
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for most GPIO bindings.
+ *
+ * Most GPIO bindings include a flags cell as part of the GPIO specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_GPIO_H
+#define _DT_BINDINGS_GPIO_GPIO_H
+
+/* Bit 0 express polarity */
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
+/* Bit 1 express single-endedness */
+#define GPIO_PUSH_PULL 0
+#define GPIO_SINGLE_ENDED 2
+
+/* Bit 2 express Open drain or open source */
+#define GPIO_LINE_OPEN_SOURCE 0
+#define GPIO_LINE_OPEN_DRAIN 4
+
+/*
+ *  * Open Drain/Collector is the combination of single-ended open drain interface.
+ *   * Open Source/Emitter is the combination of single-ended open source interface.
+ *    */
+#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)
+#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)
+
+/* Bit 3 express GPIO suspend/resume persistence */
+#define GPIO_SLEEP_MAINTAIN_VALUE 0
+#define GPIO_SLEEP_MAY_LOOSE_VALUE 8
+
+#endif

--- include/dt-bindings/interrupt-controller/irq.h	1970-01-01 02:00:00.000000000 +0200
+++ include/dt-bindings/interrupt-controller/irq.h	2021-11-09 17:10:27.966356000 +0200
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for most IRQ bindings.
+ *
+ * Most IRQ bindings include a flags cell as part of the IRQ specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
+
+#define IRQ_TYPE_NONE		0
+#define IRQ_TYPE_EDGE_RISING	1
+#define IRQ_TYPE_EDGE_FALLING	2
+#define IRQ_TYPE_EDGE_BOTH	(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
+#define IRQ_TYPE_LEVEL_HIGH	4
+#define IRQ_TYPE_LEVEL_LOW	8
+
+#endif

--- include/dt-bindings/media/xilinx-vip.h	1970-01-01 02:00:00.000000000 +0200
+++ include/dt-bindings/media/xilinx-vip.h	2021-11-09 17:10:27.966356000 +0200
@@ -0,0 +1,39 @@
+/*
+ * Xilinx Video IP Core
+ *
+ * Copyright (C) 2013-2015 Ideas on Board
+ * Copyright (C) 2013-2015 Xilinx, Inc.
+ *
+ * Contacts: Hyun Kwon <hyun.kwon@xilinx.com>
+ *           Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_MEDIA_XILINX_VIP_H__
+#define __DT_BINDINGS_MEDIA_XILINX_VIP_H__
+
+/*
+ * Video format codes as defined in "AXI4-Stream Video IP and System Design
+ * Guide".
+ */
+#define XVIP_VF_YUV_422			0
+#define XVIP_VF_YUV_444			1
+#define XVIP_VF_RBG			2
+#define XVIP_VF_YUV_420			3
+#define XVIP_VF_YUVA_422		4
+#define XVIP_VF_YUVA_444		5
+#define XVIP_VF_RGBA			6
+#define XVIP_VF_YUVA_420		7
+#define XVIP_VF_YUVD_422		8
+#define XVIP_VF_YUVD_444		9
+#define XVIP_VF_RGBD			10
+#define XVIP_VF_YUVD_420		11
+#define XVIP_VF_MONO_SENSOR		12
+#define XVIP_VF_CUSTOM2			13
+#define XVIP_VF_CUSTOM3			14
+#define XVIP_VF_CUSTOM4			15
+
+#endif /* __DT_BINDINGS_MEDIA_XILINX_VIP_H__ */

--- include/dt-bindings/net/ti-dp83867.h	1970-01-01 02:00:00.000000000 +0200
+++ include/dt-bindings/net/ti-dp83867.h	2021-11-09 17:10:27.966356000 +0200
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Device Tree constants for the Texas Instruments DP83867 PHY
+ *
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * Copyright:   (C) 2015 Texas Instruments, Inc.
+ */
+
+#ifndef _DT_BINDINGS_TI_DP83867_H
+#define _DT_BINDINGS_TI_DP83867_H
+
+/* PHY CTRL bits */
+#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB	0x00
+#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB	0x01
+#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB	0x02
+#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB	0x03
+
+/* RGMIIDCTL internal delay for rx and tx */
+#define	DP83867_RGMIIDCTL_250_PS	0x0
+#define	DP83867_RGMIIDCTL_500_PS	0x1
+#define	DP83867_RGMIIDCTL_750_PS	0x2
+#define	DP83867_RGMIIDCTL_1_NS		0x3
+#define	DP83867_RGMIIDCTL_1_25_NS	0x4
+#define	DP83867_RGMIIDCTL_1_50_NS	0x5
+#define	DP83867_RGMIIDCTL_1_75_NS	0x6
+#define	DP83867_RGMIIDCTL_2_00_NS	0x7
+#define	DP83867_RGMIIDCTL_2_25_NS	0x8
+#define	DP83867_RGMIIDCTL_2_50_NS	0x9
+#define	DP83867_RGMIIDCTL_2_75_NS	0xa
+#define	DP83867_RGMIIDCTL_3_00_NS	0xb
+#define	DP83867_RGMIIDCTL_3_25_NS	0xc
+#define	DP83867_RGMIIDCTL_3_50_NS	0xd
+#define	DP83867_RGMIIDCTL_3_75_NS	0xe
+#define	DP83867_RGMIIDCTL_4_00_NS	0xf
+
+/* IO_MUX_CFG - Clock output selection */
+#define DP83867_CLK_O_SEL_CHN_A_RCLK		0x0
+#define DP83867_CLK_O_SEL_CHN_B_RCLK		0x1
+#define DP83867_CLK_O_SEL_CHN_C_RCLK		0x2
+#define DP83867_CLK_O_SEL_CHN_D_RCLK		0x3
+#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5	0x4
+#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5	0x5
+#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5	0x6
+#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5	0x7
+#define DP83867_CLK_O_SEL_CHN_A_TCLK		0x8
+#define DP83867_CLK_O_SEL_CHN_B_TCLK		0x9
+#define DP83867_CLK_O_SEL_CHN_C_TCLK		0xA
+#define DP83867_CLK_O_SEL_CHN_D_TCLK		0xB
+#define DP83867_CLK_O_SEL_REF_CLK		0xC
+/* Special flag to indicate clock should be off */
+#define DP83867_CLK_O_SEL_OFF			0xFFFFFFFF
+#endif

--- include/dt-bindings/phy/phy.h	1970-01-01 02:00:00.000000000 +0200
+++ include/dt-bindings/phy/phy.h	2021-11-09 17:10:27.966356000 +0200
@@ -0,0 +1,22 @@
+/*
+ *
+ * This header provides constants for the phy framework
+ *
+ * Copyright (C) 2014 STMicroelectronics
+ * Author: Gabriel Fernandez <gabriel.fernandez@st.com>
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#ifndef _DT_BINDINGS_PHY
+#define _DT_BINDINGS_PHY
+
+#define PHY_NONE		0
+#define PHY_TYPE_SATA		1
+#define PHY_TYPE_PCIE		2
+#define PHY_TYPE_USB2		3
+#define PHY_TYPE_USB3		4
+#define PHY_TYPE_UFS		5
+#define PHY_TYPE_DP		6
+#define PHY_TYPE_SGMII		7
+
+#endif /* _DT_BINDINGS_PHY */

--- system-top.dts	2022-01-19 21:37:07.824336155 +0200
+++ system-top.dts	2022-01-19 21:39:20.616332170 +0200
@@ -10,9 +10,10 @@
 #include "zynqmp-clk-ccf.dtsi"
 #include "pl.dtsi"
 #include "pcw.dtsi"
+#include "system-user.dtsi"
 / {
 	chosen {
-		bootargs = "earlycon";
+		bootargs = "console=ttyPS0,115200 earlyprintk earlycon clk_ignore_unused";
 		stdout-path = "serial0:115200n8";
 	};
 	aliases {

--- system-user.dtsi	1970-01-01 02:00:00.000000000 +0200
+++ system-user.dtsi	2022-01-19 21:40:30.108330084 +0200
@@ -0,0 +1,354 @@
+#include "include/dt-bindings/interrupt-controller/irq.h"
+#include "include/dt-bindings/gpio/gpio.h"
+#include "include/dt-bindings/media/xilinx-vip.h"
+#include "include/dt-bindings/net/ti-dp83867.h"
+#include "include/dt-bindings/phy/phy.h"
+
+/ {
+};
+
+&sdhci1 {
+	disable-wp;
+	xlnx,itap-delay-sd-hsd = <0x29>;
+	xlnx,itap-delay-sd-ddr50 = <0x32>;
+	xlnx,itap-delay-sdr25 = <0x2A>;
+	xlnx,itap-delay-sdr50 = <0x1E>;
+	xlnx,itap-delay-sdr104 = <0x0B>; //although auto-tuned, tuning fails on some cards if not set
+};
+
+/*
+devicetree/bindings/net/macb.txt
+devicetree/bindings/net/ti,dp83867.txt
+devicetree/bindings/net/phy.txt
+*/
+&gem0 {
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+	phy0: phy@15 {
+		reg = <0x0F>;
+		reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
+		reset-assert-us = <1>;
+		reset_deassert-us = <200>;
+		interrupt-parent = <&gpio>;
+		interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; //overwrites strap config
+		ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; //overwrites strap config
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+		ti,clk-output-sel = <DP83867_CLK_O_SEL_REF_CLK>;
+	};
+};
+
+
+/*
+Adding support for the mux and expose all 8 segments.
+RESET# pin of TCA9548 is inverted on-board. Mapped to
+EMIO[0] which is line 78.
+*/
+&i2c0 {
+	i2c-mux@70 {
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x70>;
+		reset-gpios = <&gpio 78 GPIO_ACTIVE_HIGH>;
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+		};
+		i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+		};
+		i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+		};
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+			pmu@43 { /* IRPS5401 - IC81 */
+				#clock-cells = <0>;
+				compatible = "infineon,irps5401";
+				reg = <0x43>; /*PMBUS address*/
+			};
+			pmu@44 { /* IRPS5401 - IC83 */
+				#clock-cells = <0>;
+				compatible = "infineon,irps5401";
+				reg = <0x44>; /*PMBUS address*/
+			};
+			pmu@45 { /* IRPS5401 - IC84 */
+				#clock-cells = <0>;
+				compatible = "infineon,irps5401";
+				reg = <0x45>; /*PMBUS address*/
+			};
+		};
+		i2c@4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <4>;
+			eeprom@51 { /*FMC VITA 57.1 FRU*/
+				compatible = "atmel,24c02";
+				reg = <0x51>;
+				pagesize = <1>; /* varies between models, so use a safe value */
+			};
+		};
+		i2c@5 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <5>;
+			/* not sure if we should bind the eeprom driver to the SYZYGY DNA */
+			eeprom@30 { /* SYZYGY DNA */
+				compatible = "atmel,24c02";
+				reg = <0x30>;
+				read-only;
+				address-width = <16>;
+				size = <65536>; /*the whole 16-bit address range*/
+			};
+		};
+		i2c@6 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <6>;
+		};
+		i2c@7 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <7>;
+		};
+	};
+};
+
+&spi0 {
+	gpioexp: gpio@1 {
+		compatible = "microchip,mcp23s08";
+		gpio-controller;
+		#reset-cells = <1>;
+		#gpio-cells = <2>;
+		interrupt-parent = <&gpio>;
+		interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
+		microchip,spi-present-mask = <0x01>;
+		interrupt-controller;
+		#interrupt-cells = <0x2>;
+		reg = <1>; /*SS[1]*/
+		spi-max-frequency = <10000000>;
+	};
+	wilc_spi@0 {
+		compatible = "microchip,wilc1000", "microchip,wilc3000";
+		spi-max-frequency = <48000000>;
+		reg = <0>;
+		irq-gpios = <&gpioexp 1 0>;
+		reset-gpios = <&gpioexp 2 0>;
+		chip_en-gpios = <&gpioexp 0 0>;
+		status = "okay";
+	};
+};
+
+&qspi {
+	u-boot,dm-pre-reloc;
+};
+
+
+&ams_pl {
+	xlnx,ext-channels {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		channel@0 {
+			reg = <0>;
+		};
+		channel@5 {
+			reg = <5>;
+		};
+		channel@6 {
+			reg = <6>;
+		};
+		channel@7 {
+			reg = <7>;
+		};
+		channel@8 {
+			reg = <8>;
+		};
+	};
+};
+
+&gpio {
+	gpio-line-names =
+	"gpio0",
+	"gpio1",
+	"gpio2",
+	"gpio3",
+	"gpio4",
+	"gpio5",
+	"gpio6",
+	"gpio7",
+	"gpio8",
+	"gpio9",
+	"btn1",
+	"btn0",
+	"gpio12",
+	"gpio13",
+	"gpio14",
+	"gpio15",
+	"gpio16",
+	"gpio17",
+	"gpio18",
+	"gpio19",
+	"gpio20",
+	"led0",
+	"gpio22",
+	"gpio23",
+	"gpio24",
+	"gpio25",
+	"gpio26",
+	"gpio27",
+	"gpio28",
+	"gpio29",
+	"gpio30",
+	"gpio31",
+	"gpio32",
+	"gpio33",
+	"gpio34",
+	"gpio35",
+	"gpio36",
+	"gpio37",
+	"gpio38",
+	"gpio39",
+	"gpio40",
+	"gpio41",
+	"gpio42",
+	"gpio43",
+	"gpio44",
+	"gpio45",
+	"gpio46",
+	"gpio47",
+	"gpio48",
+	"gpio49",
+	"gpio50",
+	"gpio51",
+	"gpio52",
+	"gpio53",
+	"gpio54",
+	"gpio55",
+	"gpio56",
+	"gpio57",
+	"gpio58",
+	"gpio59",
+	"gpio60",
+	"gpio61",
+	"gpio62",
+	"gpio63",
+	"gpio64",
+	"gpio65",
+	"gpio66",
+	"gpio67",
+	"gpio68",
+	"gpio69",
+	"gpio70",
+	"gpio71",
+	"gpio72",
+	"gpio73",
+	"gpio74",
+	"gpio75",
+	"gpio76",
+	"gpio77",
+	"iic_mux_reset",
+	"mipiA_pwup",
+	"mipiB_pwup",
+	"gpio81",
+	"gpio82",
+	"gpio83",
+	"gpio84",
+	"gpio85",
+	"gpio86",
+	"gpio87",
+	"gpio88",
+	"gpio89",
+	"gpio90",
+	"gpio91",
+	"gpio92",
+	"gpio93",
+	"gpio94",
+	"gpio95",
+	"gpio96",
+	"gpio97",
+	"gpio98",
+	"gpio99",
+	"gpio100",
+	"gpio101",
+	"gpio102",
+	"gpio103",
+	"gpio104",
+	"gpio105",
+	"gpio106",
+	"gpio107",
+	"gpio108",
+	"gpio109",
+	"gpio110",
+	"gpio111",
+	"gpio112",
+	"gpio113",
+	"gpio114",
+	"gpio115",
+	"gpio116",
+	"gpio117",
+	"gpio118",
+	"gpio119",
+	"gpio120",
+	"gpio121",
+	"gpio122",
+	"gpio123",
+	"gpio124",
+	"gpio125",
+	"gpio126",
+	"gpio127",
+	"gpio128",
+	"gpio129",
+	"gpio130",
+	"gpio131",
+	"gpio132",
+	"gpio133",
+	"gpio134",
+	"gpio135",
+	"gpio136",
+	"gpio137",
+	"gpio138",
+	"gpio139",
+	"gpio140",
+	"gpio141",
+	"gpio142",
+	"gpio143",
+	"gpio144",
+	"gpio145",
+	"gpio146",
+	"gpio147",
+	"gpio148",
+	"gpio149",
+	"gpio150",
+	"gpio151",
+	"gpio152",
+	"gpio153",
+	"gpio154",
+	"gpio155",
+	"gpio156",
+	"gpio157",
+	"gpio158",
+	"gpio159",
+	"gpio160",
+	"gpio161",
+	"gpio162",
+	"gpio163",
+	"gpio164",
+	"gpio165",
+	"gpio166",
+	"gpio167",
+	"gpio168",
+	"gpio169",
+	"gpio170",
+	"gpio171",
+	"gpio172",
+	"gpio173";
+
+};
